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WM5615
Production Data January 1997 Rev 2
10-Bit Digital-to-Analogue Converter
Description
The WM5615 is a 10-bit voltage output digital-toanalogue converter (DAC) with a buffered reference input (high impedance). The DAC produces a maximum output voltage that is twice the reference voltage and the DAC is monotonic. The device is simple to use, running from a single supply of 5V. A power-on reset function is incorporated to ensure repeatable start-up conditions. Digital control of the WM5615 is over a 3-wire serial bus that is CMOS compatible and easily interfaced to industry standard microprocessor and microcontroller devices. The device receives a 16-bit data word to produce the analogue output. The digital inputs feature Schmitt triggers for high noise immunity. Digital communication protocols include the SPI TM, QSPITM and MicrowireTM standards. The 8-terminal small-outline D package allows digital control of analogue functions in space-critical applications. The WM5615C is characterised for operation from 0oC to 70oC. The WM5615I is for operation from -40oC to 85oC.
SPI and QSPI are trademarks of Motorola, Inc. Microwire is a trademark of National Semiconductor Corp.
Features
* * * * * * * * * * * 10-bit CMOS voltage output DAC in an 8-terminal package 5V single supply operation 3-wire serial interface High-impedance reference input Maximum voltage output twice reference input voltage Internal power-on reset Low power consumption ... 1.75mW max 877kHz update rate Setting time to 0.5 LSB ... 12.5s typical Monotonic over temperature Pin compatible with the Maxim MAX515
Applications
* * * * * Battery-powered test Instruments Digital offset and gain adjustment Battery-operated/remote industrial controls Machine and motion control devices Cellular telephones
Block Diagram
+ REFIN
5
VOUT R R VDD
+
AGND POWER-ON RESET
RESISTOR STRING DAC
-
10-BIT DAC REGISTER CS SCLK 2 Xs DIN CONTROL LOGIC (LSB) (MSB) 4 DUMMY BITS
DOUT
16-BIT SHIFT REGISTER
Production Data data sheets contain final specifications current on publication date. Supply of products conforms to Wolfson Microelectronics standard terms and conditions.
Wolfson Microelectronics
Lutton Court, Bernard Terrace, Edinburgh EH8 9NX. UK
(c) 1996 Wolfson Microelectronics
Tel: +44 (0) 131 667 9386 Fax: +44 (0) 131 667 5176 email: admin@wolfson.co.uk www: http://www.wolfson.co.uk
WM5615
Pin Configuration
D or P package Top View
DIN 1 SCLK 2 CS 3 DOUT 4 8 VDD 7 VOUT 6 REFIN 5 AGND
Ordering Information
DEVICE WM5615CD WM5615CP WM5615ID WM5615IP TEMP RANGE 0oC to +70oC 0oC to +70oC -40oC to +85oC -40oC to +85oC PACKAGE 8 pin SO 8 pin DIP 8 pin SO 8 pin DIP
Absolute Maximum Ratings
Supply voltage (VDD to AGND) . . . . . . . . . . . . 7V Digital input voltage range to AGND . .-0.3V to VDD +0.3V Ref. input voltage range to AGND . . .-0.3V to VDD + 0.3V Output voltage at OUT from external source . .VDD + 0.3V Continuous current, any terminal . . . . . . . . 20mA Operating free-air temperature range TA: WM5615C . . . . . . . . . . . . . . . . . . 0 oC to +70o C WM5615I . . . . . . . . . . . . . . . . . -40o C to +85o C Storage temperature range Tstg . . . . . -65o C to +150oC Lead temperature 1.6mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . .260o C
Note:
Stresses beyond those listed under 'Absolute Maximum Ratings' may cause damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under 'Recommended Operating Conditions' is not implied. Exposure to absolute maximum rated conditions for extended periods may affect device reliability.
Recommended Operating Conditions
PARAMETER Supply voltage High-level digital input voltage Low-level digital input voltage Reference voltage to REFIN terminal Load resistance Operating free air temperature SYMBOL VDD VIH VIL Vref RL TA TA MIN 4.5 2.4 0 2 0 -40 TYP 5 MAX 5.5 0.8 VDD-2 70 85 UNIT V V V V k o C o C
2.048
WM5615C WM5615I
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WM5615
Electrical Characteristics
Static DAC Specifications
PARAMETER Resolution Integral nonlinearity Differential nonlinearity Zero scale error (offset error) Zero scale error (offset error) temperature coefficient Gain error Gain error temperature coefficient Power-supply rejection ratio Analogue full scale output SYMBOL INL DNL EZS (see (see (see (see CONDITIONS note note note note 1) 2) 3) 4) MIN 10 +0.1 3 3 1 0.1 0.1 2Vref(1023/1024) 1 0.5 3 TYP MAX UNIT bits LSB LSB LSB ppm/oC LSB ppm/oC LSB/V V (over recommended operating free-air temperature range) VDD = 5.0V 5%, Vref = 2.048V unless otherwise stated.
EG
(see note 5) (see note 6) Offset (see notes 7 and 8) Gain RL = 100k
PSRR
Notes: 1. The relative accuracy or integral nonlinearity (INL), sometimes referred to as linearity error, is the maximum deviation ot the output from the line between zero and full scale, excluding the effect of zero code and full scale errors (see text). 2. The differential nonlinearity (DNL), sometimes referred to as differential error, is the difference between the measured and ideal LSB amplitude change of any two adjacent codes. Monotonic means the output voltage changes in the same direction (or remains constant) as a change in the digital input code. 3. Zero-scale error is the deviation from zero voltage output when the digital input is zero (see text) 4. Zero-scale error temperature coefficient is given by EZS TC = [EZS (Tmax) - EZS (Tmin)] /Vref x 106/ (TmaxTmin)
5. Gain error is the deviation from the ideal output (Vref - 1LSB) with an output load of 10k, excluding the effects of zero error. 6. Gain temperature coefficient is given by EG TC = [EG (Tmax) - EG (Tmin)] /Vref x 106/(Tmax-Tmin). 7. Zero-scale offset error rejection ratio (EZS-RR) is measured by varying the VDD from 4.5V to 5.5V DC and measuring the proportion of this signal imposed on the zero-code output voltage. 8. Gain error rejection ratio (EG-RR) is measured by varying the VDD from 4.5 to 5.5 V DC and measuring the proportion of this signal imposed on the full-scale output voltage after subtracting the zero scale change.
Voltage Output (OUT)
PARAMETER Voltage output range Output load regulation accuracy Output short circuit current Output voltage, low level Output voltage, high level SYMBOL VO IOSC VOL(low) VOH(high) CONDITIONS RL = 10k VO(OUT) = 2V RL=2k OUT to VDD or AGND IO (OUT) <= 5mA IO (OUT) <= -5mA MIN 0 TYP MAX VDD-0.4 0.5 0.25 4.75 UNIT V LSB mA V V
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WM5615
Electrical Characteristics (continued)
VDD = 5.0V 5%, Vref = 2.048V unless otherwise stated.
Reference Input (REFIN)
PARAMETER Input voltage range Input resistance Input capacitance SYMBOL VI CI CONDITIONS MIN 0 10 TYP MAX VDD-2 UNIT V M pF
5
Digital Inputs (DIN, SCLK, CS)
PARAMETER High level digital input voltage Low level digital input voltage High level digital input current Low level digital input current Input capacitance SYMBOL CONDITIONS VIH VIL IIH VI = VDD IIL VI = 0V CI MIN 2.4 TYP MAX 0.8 1 1 8 UNIT V V A A pF
Digital Output (DOUT)
PARAMETER Output voltage high Output voltage low SYMBOL CONDITIONS VOH IO = -2mA VOL IO = 2mA MIN VDD-1 TYP MAX 0.4 UNIT V V
Power Supply
PARAMETER Supply voltage Power supply current SYMBOL VDD IDD CONDITIONS VDD = 5.5V, no load. Vref = 0V All inputs = 0V or VDD VDD = 5.5V, no load. Vref = 2.048V All inputs = 0V or VDD MIN 4.5 TYP 5 150 230 MAX 5.5 250 350 UNIT V A A
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WM5615
Electrical Characteristics (continued) VDD = 5.0V 5%, Vref = 2.048V unless otherwise stated.
Analogue Output Dynamic Performance
PARAMETER Output slew rate Output settling time Glitch energy Signal to noise + distortion SYMBOL CONDITIONS SR CL = 100pF RL = 10 k TA = 25oC TO 0.5 LSB CL = 100pF tS RL = 2k (see note 9) DIN = All 0s to all 1s S/(N+D) Vref = 2Vpp at 1kHz + 2.048 V DC, code 512 MIN 0.3 TYP 0.5 12.5 5 60 MAX UNIT V/s s nV. s dB
Note 9:
Settling time is the time for the output signal to remain within 0.5 LSB of the final measured value for a digital input code change from code zero to 1023 rising and 1023 to 64 falling.
Digital Input Timing Specifications
PARAMETER Setup time, DIN before SCLK high Hold time, DIN valid after SCLK high Setup time, CS low to SCLK high Setup time CS high to SCLK high Hold time, SCLK low to CS low Hold time, SCLK low to CS high Pulse duration, min. chip select pulse width height Pulse duration, SCLK low Pulse duration, SCLK high SYMBOL tsu (DS) th (DH) tsu (CSS) tsu (CS1) th (CSHO) th (CSHI) tw(CS) tw (CL) tw (CH) MIN 45 0 1 50 1 0 20 18 18 TYP MAX UNIT ns ns ns ns ns ns ns ns ns
Output Switching Specification
PARAMETER Propagation delay time SYMBOL tpd (DOUT) CONDITIONS CL = 50pF MIN TYP MAX 50 UNIT ns
reference input (REFIN)
PARAMETER Reference feedthrough Reference input bandwidth CONDITIONS Input code = 00 (see note 10) Input code = 512 (see note 10) MIN TYP -80 100 MAX UNIT dB kHz
Note 10: Reference feedthrough and bandwidth are measured at the DAC output with Vref input = 2Vpp at 1kHz + 2.048V DC
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WM5615
Typical Performance Characteristics
0.2
0.15
0.1
0.05
LSB LSBs
0
-0.05
-0.1
-0.15
1
256
511
766
0
256
512 INPUT CODE
768
1024
WM5615 DNL Linearity Error
1 0.8 0.6 0.4 0.2 0
LSB
-0.2 -0.4 -0.6 -0.8 -1 1 256 511 766 0 256 512 INPUT CODE 768 1024 1021
WM5615 INL Linearity Error
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1021
-0.2
WM5615 Pin Description
PIN 1 2 3 4 5 6 7 8 NAME DIN SCLK CS DOUT AGND REFIN VOUT VDD FUNCTION Serial data input. Serial clock input. Chip select, active low. Serial data output for daisychaining. Analogue ground. Reference input. DAC output. Positive power supply.
Timing Diagram
CS th(CSHO) tsu(CSS) tw(CH) SCLK th(DH) tsu(DS) DIN tw(CS) tw(CL) th(CSH1) tsu(CS1)
See note C
See note A
See note B
DOUT
tpd(DOUT)
Previous LSB
NOTES: A. The input clock, applied at the SCLK terminal, should be inhibited low when CS is high to minimise clock feedthrough. B. Data input from preceeding conversion cycle. C. Sixteenth SCLK falling edge.
Detailed Description
General Function The WM5615 uses a resistor string network buffered with a single-supply CMOS op amp in a fixed gain of x2 to convert 10-bit digital data to analogue voltage levels (see Block Diagram). The topology of the WM5615 makes the output the same polarity as the reference input (see Table 1). An internal reset circuit forces the DAC register to reset to all 0s on power-up.
AGND 0.1F +5V DIN REFIN SCLK CS DOUT
+ + R VOUT
R
VDD
Figure 1 - Typical Operating Circuit
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WM5615
Detailed Description (Continued)
Table 1 - Binary Code Table (0V to 2VREFIN Output), Gain = 2 INPUT* 1111 1111 11 (xx) OUTPUT 1023 +2(VREFIN) 1024 Serial Interface The WM5615 uses a three-wire serial interface which is compatible with SPI, QSPI (CPOL = CPHA = 0) and Microwire standards as shown in figures 2 and 3. The DAC is programmed by writing two 8-bit words, MSB first (see Block Diagram and Timing Diagram). 16 bits of serial data are clocked into the DAC in the following order, 4 fill (dummy) bits, 10 data bits and 2 sub-LSB Xs. The 4 dummy bits are not normally needed and are required only when DACs are daisy chained. The 2 subLSB Xs, however, are always needed because the input register is 12 bits wide. Transitions at CS should occur while SCLK is low. Data is clocked in on the SCLK rising edge while CS is low. The serial input data is held in a 16bit serial shift register. On the CS rising edge, the ten data-bits are transferred to the DAC register and update the DAC. With CS high, data cannot be clocked into the DIN terminal. The WM5615 receives data in 16-bit blocks. The SPI and Microwire interfaces output data in 8-bit blocks requiring two write cycles to input data to the DAC. The QSPI interface allows variable data output from 8 to 16 bits so can load into the DAC in one write cycle.
513 1000 0000 01 (xx) +2(VREFIN) 1024 512 1000 0000 00 (xx) +2(VREFIN) 1024 = V REFIN 511 1024 1 0000 0000 01 (xx) +2(VREFIN) 1024 0111 1111 11 (xx) +2(VREFIN) 0000 0000 00 (xx) 0V
* A 10-bit data word with two sub-LSB Xs must be written since the DAC input latch is 12-bits wide.
Buffer Amplifier The output buffer is a rail-to-rail output CMOS op amp. Max. setting time is 12.5s to +/-0.5 LSB of final value. The output is short-circuit protected and can drive a 2k load with a 100pF load capacitance. External Reference The external voltage input is buffered and must be positive but less than VDD - 2V. The reference voltage determines the DAC full-scale output. Since the reference terminal is buffered, the DAC input resistance is not code dependent and is 10M minimum. The REFIN input capacitance is typically 5pF. Digital Interface The digital inputs are designed to be compatible with TTL or CMOS logic levels. However, to achieve the lowest power dissipation, the digital inputs should be driven with rail-to-rail CMOS logic. With TTL logic levels, the power requirement increases by a factor of approximately two.
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WM5615
Detailed Description (Continued)
SCLK SK SCLK SCK
WM5615
DIN
SO I/O
Microwire Port
WM5615
DIN
MOSI I/O
CS
CS
SPI Port
DOUT
SI
DOUT
MISO
Figure 2 - Microwire Connection
Figure 3 - SPI/QSPI Connection
Note: The DOUT-MISI connection is not required for writing to the WM5615, but may be used for verifying data transfer. Daisy-Chaining Devices The serial output, DOUT, allows cascading of two or more DACs. The data at DIN appears at DOUT, delayed by 16 clock cycles plus one clock width. For low power, DOUT does not require an external pull-up resistor. DOUT does not go into a high-impedance state when CS is high. DOUT changes on SCLK's falling edge when CS is low. When CS is high, DOUT remains in the state of the last data bit. Any number of DACs can be daisy-chained by connecting the DOUT of one device to the DIN of the next device in the chain. Linearity, Offset and Gain Error using Single End Supplies When an amplifier is operated from a single supply, the voltage offset can still be either positive or negative. With a positive offset, the output voltage changes on the first code change. With a negative offset, the output voltage may not change with the first code depending on the magnitude of the offset voltage. The output amplifier, with a negative voltage offset, attempts to drive the output to a negative voltage. However, because the most negative supply rail is ground, the output cannot drive to a negative voltage. So when the output offset voltage is negative, the output voltage remains at zero volts until the input code value produces a sufficient output voltage to overcome the inherent negative offset voltage, resulting in the transfer function shown in figure 4.
Output Voltage
DAC Code Negative Offset
Figure 4 - Effect of Negative Offset (Single Supply) This negative offset, not the linearity error, produces this breakpoint. The transfer function would have followed the dotted line if the output buffer could drive to a negative voltage. For a DAC, linearity is measured between zero input code (all inputs 0) after offset and full-scale are adjusted out or accounted for in some way. However, single supply operation does not allow for adjustment when the output is negative due to the breakpoint in the transfer function. So the linearity is measured between the full-scale and the lowest code which produces a positive output voltage. For the WM5615, the zero scale (offset) is plus or minus 3LSB maximum. The code is calculated from the maximum specification for the negative offset.
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WM5615
Detailed Description (Continued)
Power-Supply Bypassing and Ground Management Best system performance is obtained with printed-circuit boards that use separate analog and digital ground planes. Wire-wrap boards are not recommended. The two ground planes should be connected together at the lowimpedance power-supply source. The best ground connection may be achieved by connecting the DAC AGND terminal to the system analogue ground plane. VDD should be bypassed with a 0.1F ceramic capacitor connected between VDD and AGND. It should be mounted with short leads close to the device. Ferrite beads may be used to further isolate the system analogue and digital power supplies. Figure 5 illustrates the grounding and bypassing scheme described. Analogue Feedthrough Because of internal stray capacitance, higher frequency analog input signals may couple to the output. this is tested by holding CS high, setting the DAC code to all 0s and sweeping REFIN. Digital Feedthrough High-speed serial data at any of the digital input or output pins may couple through the DAC package internal stray capacitance to appear at the DAC output as noise, even though CS is held high. This digital feedthrough is tested by holding CS high while transmitting 1010... from DIN to DOUT.
Analogue Ground Plane
1 2 3 4
8 7 6 5
0.1 F
Figure 5 - Power-Supply Bypassing
Saving Power When the DAC is not being used by the system, minimize power consumption by setting the appropriate code to minimize load. For example, with a resistive load to ground, set the DAC code to 0 (see Table 1). In addition, the REFIN buffer has to drive current into the DAC resistor string and so setting REFIN to 0 further reduces power consumption.
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WM5615
Package Descriptions
Plastic Small-Outline Package D - 8 pins shown
4.00 3.80 8
A 5
6.20 5.80
1 1.75 1.35
4 0.50 0.25 0.19 x 45O NOM 0.25
0.51 0.25 0.10 0.33 Pin spacing 1.27 B.S.C. 0O to 8O 1.27 0.40
Dimension 'A' Variations N 8 14 16 Min 4.80 8.55 9.80 Max 5.00 8.75 10.00
Notes: A . Dimensions in millimeters. B. Complies with Jedec standard MS-012. C. This drawing is subject to change without notice. D. Body dimensions do not include mold flash or protrusion. E. Dimension A, mould flash or protrusion shall not exceed 0.15mm. Body width, interlead flash or protrusions shall not exceed 0.25mm.
Rev. 1 November 96
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WM5615
Package Descriptions
Dual-In-Line Package
N or P
N
0.325 0.290 0.015 Min.
1
N/2
A 0.070 Max.
0.280 0.240
0.210 Max. 105O 90O 0.014 0.008 0.150 0.115 0.005 Min. Pin spacing 0.100 B.S.C. 0.045 0.030 0.022 0.014 Seating plane
Dimension 'A' Variations N 8 14 16 20 Min 0.355 0.735 0.735 0.940 Max 0.400 0.775 0.775 0.975
Notes: A . Dimensions are in inches B. Falls within JEDEC MS-001( 20 pin package is shorter than MS-001) C. N is the maximum number of terminals D. All end pins are partial width pins as shown, except the 14 pin package which is full width.
Rev. 1 November 96
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